Physical Design Engineer

Job Title

Physical Design Engineer

Role Summary

Join a team responsible for block- and top-level physical implementation of ASIC/SoC designs. The role focuses on floorplanning, place-and-route, timing closure, signal/power integrity, and shipping hard-macros from netlist to GDS with physical verification.

Experience Level

Senior — typically 8–10 years of relevant physical design experience.

Responsibilities

Primary responsibilities for this role include implementation and closure of complex top-level and block-level designs.

• Create and execute floorplans for blocks and top level, including power planning.
• Perform placement, clock tree synthesis (CTS), routing, and timing closure.
• Analyze and mitigate signal integrity (SI) and power integrity (I/R drop) issues.
• Use P&R flows to take hard-macros from netlist through GDS, including timing closure and physical verification (PV).
• Run and interpret static timing analysis and fix timing issues across hierarchical/top-level modules.
• Collaborate with verification, architecture, and EDA/tool teams to resolve implementation issues.
• Maintain design documentation and participate in design reviews.

Requirements

Must-have technical skills and experience; concise list of required and preferred qualifications.

• Must-have: 8+ years in physical design with strong experience in floorplanning, placement, CTS, routing, and timing closure at block and top level.
• Must-have: Hands-on experience with Synopsys implementation tools (Design Compiler / IC Compiler flows), LINT, PTSI, and scripting for flows.
• Must-have: Experience with Verilog or VHDL netlists and taking designs from netlist to GDS.
• Must-have: Proven ability to identify and fix SI and I/R drop issues and to close timing in complex MSM/top-level designs.
• Nice-to-have: Familiarity with power planning methodologies, advanced node P&R considerations, and physical verification tool flows.
• Nice-to-have: Prior experience coordinating cross-functional fix-it efforts and supporting product/test phases.
• Other (from posting): Experience with application configuration, Java extensions, or Maximo/TRM is listed in the source but appears unrelated to core PD tasks.

Education Requirements

Bachelor of Engineering (B.E.) is specified in the posting. No additional degrees, specific fields of engineering, nor "equivalent experience" language was stated.

About the Company

Company: Retym Israel

Technology company hiring VLSI/ASIC digital design engineers for communication systems and SoC/IP development. Work includes RTL design, verification, synthesis, timing closure, and silicon bring-up.