Physical Design Engineer

Job Title

Physical Design Engineer

Role Summary

Join a semiconductor engineering team responsible for RTL-to-GDSII implementation and signoff for SoC and ASIC projects. The role focuses on physical implementation, timing closure, power optimization, and tapeout readiness for advanced-node designs.

Experience Level

Mid-level — 5–15 years of relevant physical design experience preferred.

Responsibilities

Deliver physical design implementation and drive design closure across block and full-chip flows.

• Perform floorplanning, placement, clock-tree synthesis (CTS), routing, and physical verification.
• Execute static timing closure, congestion analysis, and power optimization.
• Analyze and resolve setup/hold violations and signal-integrity issues.
• Coordinate with RTL, DFT, STA, and backend teams to achieve design convergence.
• Support ECO flows and low-power implementation techniques.
• Prepare designs for tapeout and participate in signoff activities.

Requirements

Must-have technical skills and tools experience.

• Hands-on experience with full physical design flow from netlist to GDSII, including floorplanning, placement, CTS, routing, and timing closure.
• Experience with tools such as Cadence Innovus, ICC2, PrimeTime/Tempus, and Calibre (DRC/LVS).
• Knowledge of static timing analysis (STA), IR drop and EM analysis, and physical verification flows.
• Strong scripting skills in Tcl, Perl, or Python for automation and debugging.
• Proven debugging and problem-solving skills on complex SoC/ASIC projects.
• Experience working with cross-functional teams (RTL, DFT, STA, PD) to close designs.

Nice-to-have:

• Experience with advanced process nodes (7nm/5nm/3nm) and prior tapeout experience on complex SoCs.
• Familiarity with low-power design methodologies and UPF/CPF flows.
• Strong communication and collaboration skills.

Education Requirements

Not specified.

About the Company

Company: CaritaTech

Engineering staffing and consulting firm providing placement and contract services for hardware, semiconductor, and embedded systems professionals, including roles in SoC/ASIC physical design and verification.