PE Layout Design Engineer

Role Overview

The PE Layout Design Engineer role involves direct engagement in layout design within the MIC Design IDC team located in Bangalore. The candidate will report to the layout manager and play a crucial role in developing memory interface chips. The position expects collaboration with experienced engineers to enhance the functionality and efficiency of chip operations.

Experience Level

Applicants should possess between 12 to 15 years of relevant experience in electrical or electronic engineering, particularly in semiconductor layout design.

Key Responsibilities

The main responsibilities of this role include:

• Leading the layout team and managing deliverables for various projects.
• Demonstrating strong proficiency with Cadence Virtuoso XL/VXL tools and layout verification techniques such as LVS, DRC, Antenna checks, and density verifications.
• Collaborating with global teams to address and resolve layout challenges.
• Conducting floorplan, power grid, and signal planning as well as reviews.
• Managing challenges in bump-out planning and estimating die areas.
• Resolving reliability issues including EMIR, EOS, and ESD/Latchup.
• Implementing best practices in layout design such as matching, parasitic considerations, and shielding.

Qualifications

Candidates must have a degree in Electrical or Electronic Engineering with substantial hands-on experience in layout design. Familiarity with design of transmitters, receivers, PLLs, and voltage regulators is advantageous. Experience in advanced nodes (22nm to 7nm) and knowledge of scripting languages such as skill, Perl, or Tcl is desirable. A proven ability to work well in teams and stay self-motivated is essential.

Education Requirements

Must possess a degree in Electrical/Electronic Engineering or a related field.