PD Layout Engineer
Responsible for physical layout and closure of MCU/SoC designs within the MCU organization, focusing on floorplanning, congestion analysis, power‑grid design, IR‑drop validation, and DRC/LVS closure. Works with SoC design teams and uses advanced EDA tools (e.g., Innovus) to drive ECO implementations and correct‑by‑construction methodologies.
This role supports products targeting AI‑driven data centers and emerging systems and expects practical, execution‑focused contributions to layout closure and flow automation.
Mid-level — minimum 3 years of relevant experience.
Primary responsibilities include physical layout implementation, verification, and automation to achieve signoff‑ready SoC layouts.
Must-have and preferred technical skills and experience.
Bachelor's degree is indicated (Degree Level: Bachelor's Degree). Field of study not specified.
Company: Texas Instruments
Headquarters: Dallas, Texas, USA
Texas Instruments is a global semiconductor company that designs, manufactures, and sells analog and embedded processing chips for various markets including industrial, automotive, and personal electronics. The company's innovations aim to make electronics more affordable and reliable, fostering advancements in technology through each generation of semiconductors.
