PCS Design Engineer

Job Title

PCS Design Engineer

Role Summary

Work on the RTL team designing and implementing Physical Coding Sublayer (PCS) and Forward Error Correction (FEC) for RISC-V-based designs at an advanced technology node. The role involves RTL implementation, integration with Ethernet SERDES PHY and controllers, timing closure, and occasional technical leadership.

Experience Level

Mid-level. No explicit years of experience stated.

Responsibilities

Primary responsibilities include design, implementation, and integration tasks across PCS/FEC and related PHY subsystems.

• Design and implement PCS and FEC algorithms down to RTL (Verilog).
• Integrate Ethernet SERDES PHY and controller components with RTL blocks.
• Define and verify timing constraints; work on static timing closure and timing signoff tasks.
• Develop and maintain scripts and automation for design, verification, and integration flows.
• Collaborate with architecture/microarchitecture and system teams on RISC-V interfaces and block-level requirements.
• Lead or mentor small teams and coordinate cross-functional integration activities.

Requirements

Must-have technical skills and attributes.

• Fluent English (C1 level).
• Experience with timing and timing constraints for ASIC designs.
• Proficient in Verilog RTL coding and verification practices.
• Proven experience implementing PCS and FEC algorithms.
• Experience integrating Ethernet SERDES PHY and controller components.
• Scripting experience for automation (e.g., Python, TCL or similar).
• Experience leading teams or technical leadership on projects.

Nice-to-have: Strong architecture or microarchitecture background, prior work on RISC-V subsystems, and experience at advanced process nodes.

Education Requirements

Bachelor's degree in Computer Science is specified.

About the Company

Company: Semidynamics

Headquarters: Barcelona, Spain

Semidynamics is a company specializing in infrastructure verification and automation solutions. They focus on optimizing resources and enhancing continuous integration processes in design verification. The team collaborates to maintain regression test infrastructure and develop efficient workflows.