Mixed Signal Logic Design Engineer

Job Title

Mixed Signal Logic Design Engineer

Role Summary

Design RTL and verify mixed-signal and high-speed IP blocks for integration into SoCs. Work with cross-functional teams to define microarchitecture, optimize for power/performance/area, and ensure correct verification and integration of IP into full-chip designs.

Experience Level

Mid-level (typical candidate: several years of relevant RTL and mixed-signal design experience). The posting indicates 2+ years for key technical skills and degree-dependent minimum experience levels (see Education Requirements).

Responsibilities

Key responsibilities include designing, coding, verifying, and supporting mixed-signal IP for SoC integration.

• Develop RTL (SystemVerilog/Verilog) and perform block-level simulation and verification.
• Participate in architecture and microarchitecture design decisions for IP blocks.
• Model analog behavior and apply mixed-signal design strategies to meet power, performance, area, and timing goals.
• Optimize logic for low-power techniques (UPF, clock gating) and manage clock domain crossings and voltage-domain interactions.
• Review and execute verification plans; debug and resolve failing RTL tests and speed-path issues.
• Support SoC integration and collaborate with verification, physical implementation, and system teams.

Requirements

Must-have technical skills and experience. Preferred items listed separately.

Must-have:

• Proficiency in RTL design and coding using SystemVerilog and Verilog.
• Practical knowledge of mixed-signal fundamentals and low-power design (UPF, clock gating).
• Understanding of digital and analog design principles, clock-domain crossing, and power/performance tradeoffs.
• Experience with hardware simulation and debug tools (e.g., VCS, Verdi) and front-end design tools (lint, CDC, RDC, synthesis).
• Familiarity with IP environments and configuration/version-management tools.
• At least 2+ years of relevant technical experience consistent with the role's requirements.
• This position is not eligible for Intel immigration sponsorship.

Nice-to-have / Preferred:

• Experience debugging complex logic, timing speed paths, and validating system-level functionality.
• DDR/DFI/LPDDR protocol experience and DDR design domain knowledge.
• Exposure to formal property verification, pre-silicon and post-silicon validation.
• Familiarity with Git, VSCode, GitHub Copilot or other AI-assisted tools; mentoring and cross-team collaboration experience.

Education Requirements

Bachelor's (with 4+ years experience), Master's (with 3+ years), or PhD (with 1+ year) in Computer Science, Computer Engineering, Electrical Engineering or a related technical discipline. The posting indicates these qualifications may be met through combinations of industry experience, internships, coursework, or research.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.