Methodology Engineer (Silicon)

Job Title

Methodology Engineer (Silicon)

Role Summary

Build and operate the engineering methodology and automation that ensure silicon designs are specified, verified, and signed off consistently. Work with RTL, verification, physical design, and AI tooling teams to make checks, reports, and shared infrastructure that reduce manual process overhead and improve signoff reliability.

Experience Level

Mid-level. The role expects prior chip-development experience (e.g., participation in at least one tapeout) and production software engineering experience.

Responsibilities

Primary responsibilities include:

• Develop and maintain linters, static checks, and schema-driven records that validate engineering rules automatically.
• Convert CI, regression, and verification outputs into dashboards and reports that indicate block readiness for signoff.
• Implement tooling to manage exceptions and waivers so they remain owned, justified, and current across teams.
• Build shared verification libraries and flows for RTL, verification, and physical design teams.
• Define and enforce standards and checks for AI-generated code and artifacts in collaboration with AI tooling engineers.
• Analyze escaped bugs and false positives, measure process costs, and iterate on checks to reduce steps and improve accuracy.
• Collaborate cross-functionally and travel occasionally to meet teams in person.

Requirements

Must-have skills and experience:

• Proven software engineering skills; production Python and familiarity with a second language such as Rust.
• Experience with CI and build systems (e.g., GitHub Actions or similar; Bazel or another large-repo build system).
• Direct chip-development experience in design, DV, CAD, or methodology roles, including involvement in at least one tapeout.
• Sound judgment about process: able to distinguish effective rules from those that unnecessarily impede engineers.
• Clear, concise technical writing to explain rules and rationale.
• Willingness to travel a few times per year.

Nice-to-have:

• Experience with formal verification, SystemVerilog Assertions, or DV methodology.
• Familiarity with commercial lint, CDC, or formal tools and their report formats.
• Experience in traceable-evidence processes (for example DO-254 or ISO 26262).
• Experience building dashboards or data pipelines from CI and regression systems.
• Experience building tools for or integrating with AI coding agents.
• Familiarity with Bluespec or other high-level hardware description languages.

Education Requirements

Not specified.

About the Company

Company: MatX

Headquarters: Mountain View, California, USA

MatX specializes in creating faster chips for large language models (LLMs), focusing on innovative hardware and software solutions. The company fosters a collaborative and supportive work environment, welcoming candidates of all experience levels. Their approach prioritizes deep understanding and consideration of novel methods to drive efficiency and performance in their projects, particularly in silicon design and related engineering roles.