Memory PHY RTL Design Lead

Role Summary

The Memory PHY team at Advanced Micro Devices is seeking a Senior / Lead Design Engineer for RTL development focusing on high-speed LPDDR and DDR interfaces. The position involves defining, designing, and developing state-of-the-art Memory PHYs and related IP. Candidates will participate in the creation of new IO designs and improvements to existing methodologies.

Experience Level

This role is tailored for individuals with senior-level expertise in digital design engineering, specifically those accustomed to leading projects and providing mentorship within technical teams.

Responsibilities

Key responsibilities include:

• Own and implement the microarchitectural design and RTL for significant IP features and subsystems.
• Conduct synthesis, STA, CDC/RDC, design simulations, and perform power optimizations.
• Drive development initiatives from high-level architecture through to RTL coding and verification.
• Utilize and apply JEDEC DDR/LPDDR specifications for compliant PHY and controller behavior.
• Collaborate with the Firmware team to establish and enhance firmware sequences and algorithms.
• Analyze RTL designs concerning power, performance, and area; advise on optimization strategies.
• Work alongside Design Verification teams to establish comprehensive verification strategies.
• Lead design specification, microarchitecture, and RTL code review processes.
• Integrate and evaluate new EDA tools and methodologies to increase engineering productivity.
• Provide mentorship and oversee junior and intermediate engineers' day-to-day activities.
• Collaborate with other disciplines to troubleshoot and resolve complex integration issues.

Requirements

To be considered for this position, candidates should possess:

• A solid background in digital design engineering with experience in SoC/IP design.
• In-depth knowledge of DDR/LPDDR PHY and Memory Controller design.
• Competence in Verilog and SystemVerilog; familiarity with C/C++ is beneficial.
• Experience in automation and flow development scripting, preferably with Python.
• Proficiency in debugging both firmware and RTL code.
• A working understanding of UVM testbenches and verification frameworks.
• Experience in Linux development environments; Windows familiarity is advantageous.
• Understanding of clocking architectures and synchronization methods.
• Leadership experience, including managing projects and providing technical direction.

Education Requirements

A Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering is required.