Memory Layout Principal Engineer

Job Title

Memory Layout Principal Engineer

Role Summary

The Memory Layout Principal Engineer is part of the Central Engineering team at Marvell, responsible for developing advanced SoCs and high-performance memory IPs. This role involves overseeing the complete layout process for memory compilers and custom macros, ensuring technical excellence across various engineering domains.

Experience Level

Senior level, with 10-12+ years of relevant professional experience.

Responsibilities

The key responsibilities include:

• Owning the layout process for memory compilers and custom macros, including floorplanning and integration.
• Ensuring all physical and reliability checks are complete for tape-out readiness.
• Optimizing layouts for PPA targets by collaborating with circuit design and CAD teams.
• Developing scripts in Perl, Python, and SKILL to enhance verification efficiency.
• Leading layout reviews, mentoring junior engineers, and promoting best practices.
• Collaborating with foundry teams to define memory IP requirements and address technical issues.
• Contributing to memory architecture analysis and design methodology improvements.

Requirements

The candidate must meet the following criteria:

• Bachelor's, Master's, or PhD in Electrical/Electronics Engineering, Microelectronics, or related fields.
• Hands-on experience in SRAM/ROM/RF compiler layouts.
• Proven ability to design layouts from scratch, including device floorplanning and full execution.

Education Requirements

Degree in Electrical/Electronics Engineering, Microelectronics, or related fields is expected.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.