Lead Verification Engineer

Job Title

Lead Verification Engineer

Role Summary

The Lead Verification Engineer will drive functional verification for complex SoC/ASIC blocks, define verification strategy, and lead a small team of verification engineers. This role partners with RTL architects, implementation, and validation teams to ensure delivery of high-quality silicon.

Primary responsibilities include developing verification plans, creating and maintaining UVM-based environments, leading debug and closure activities, and mentoring engineers on verification methodology and best practices.

Experience Level

Senior — Lead-level engineer. Typically requires ~8+ years of verification or related ASIC/System-on-Chip experience.

Responsibilities

The core responsibilities include:

• Define verification strategy and create detailed verification plans for large digital blocks or subsystems.
• Design, develop, and maintain UVM/SystemVerilog verification environments and testbenches.
• Drive functional closure: create directed and constrained-random tests, coverage goals, and metrics tracking.
• Lead debug of functional failures across simulation, emulation, and silicon bring-up, coordinating fixes with RTL and design teams.
• Introduce and enforce verification best practices, methodologies, and automation to improve productivity.
• Mentor and coach verification engineers; oversee code reviews and project delivery schedules.
• Collaborate with architects and system teams to verify system-level interactions and integration scenarios.

Requirements

Key technical skills and experience — must-have vs nice-to-have:

• Must-have: Extensive hands-on experience with SystemVerilog and UVM, functional verification at block or subsystem level, and strong debug skills.
• Must-have: Proficiency with simulation tools and methodologies, coverage-driven verification, and scripting for automation (Python, Tcl, Perl, or similar).
• Must-have: Experience leading verification efforts and mentoring engineers; strong communication and cross-team coordination skills.
• Nice-to-have: Experience with formal verification, emulation/FPGA prototyping, low-power verification techniques, or SoC-level integration and validation.
• Nice-to-have: Background in RTL design or close collaboration with RTL designers to accelerate closure.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field is commonly required; Master's or PhD is preferred for some roles. Equivalent practical industry experience is acceptable.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.