Lead RTL Silicon Design Engineer

Role Summary

The focus of this role is to plan, build, and execute the design and validation of new and existing features for AMD’s DDR IPs.

Experience Level

Level - Senior

Responsibilities

Collaborate with cross-functional teams to design and integrate DDR memory controller calibration solutions—including RTL logic, firmware routines, and algorithmic flows—into AMD’s system-level validation and bring-up environments. Ensure seamless interaction between hardware and firmware components, delivering reliable calibration performance aligned with silicon and platform requirements.

• Design and implement robust firmware solutions for DDR memory controller calibration across various DDR standards.
• Develop and refine calibration algorithms to ensure reliable memory initialization and operation under varying process, voltage, and temperature (PVT) conditions. Focus on improving accuracy, convergence speed, and adaptability of calibration routines.
• Create and execute validation plans to verify the correctness and performance of calibration firmware and algorithms. Perform system-level bring-up and debug activities to identify and resolve issues related to memory training and stability.
• Work closely with silicon design, verification, and system engineering teams to align calibration firmware with hardware capabilities and system requirements. Ensure seamless integration and interoperability across the full memory subsystem.
• Develop clear and comprehensive documentation for calibration flows, firmware APIs, and algorithm behavior. Ensure alignment with JEDEC specifications and internal design guidelines.
• Stay updated with emerging DDR technologies and calibration techniques. Propose and implement innovative solutions to improve calibration robustness, reduce boot time, and support next-generation memory interfaces.

Requirements

B.E/M.E/M.Tech or B.S/M.S in EE/CE with 9+ years of relevant experience.

• Digital design experience with RTL design in Verilog/SystemVerilog; Knowledge of system-level architecture including buses like AXI/AHB, bridges.
• Circuit timing/STA, and practical experience with tools.
• Working knowledge of C; embedded experience a plus.
• Understanding of memory technologies such as DDR4, DDR5, LPDDR, and JEDEC standards.
• Exposure to memory controller and PHYs from different IP vendors.
• Experience with implementing DRAM/memory controller initialization code, memory subsystem/DDR PHYs training/calibration software.
• Version control systems such as Perforce, ICManage, or Git.
• Familiarity with industry standard lab tools (such as high-speed scopes, compliance packages, logic analyzers) is a plus.
• Strong verbal and written communication skills.
• Experience working in geographically dispersed teams and a strong team player.

Education Requirements

Bachelors or Masters degree in computer engineering/Electrical Engineering with 8+ years of experience.