Lead RTL Design Engineer

Role Summary

This position involves designing and executing RTL designs for PCIe technologies aimed at acceleration, AI, and data center markets. Candidates will work within the AECG Product Validation and Solutions Team at AMD, focusing on developing next-generation technologies.

Experience Level

This role is suitable for candidates with significant experience, specifically those with over 8 years in areas related to digital design and verification, particularly in a leadership capacity.

Responsibilities

The responsibilities of the Lead RTL Design Engineer include:

• Developing and productizing advanced PCIe, CXL, and connectivity solutions.
• Leading all phases of the product development cycle, from architectural design through to implementation and validation.
• Creating and executing comprehensive testing plans including compliance and interoperability testing.
• Performing pre-silicon and post-silicon validation for new PCIe-enabled blocks.
• Collaborating with global teams to enhance product features and performance.

Requirements

Candidates must meet the following requirements:

• Proficient in RTL coding, specifically with Verilog and SystemVerilog.
• Experience using RTL simulation tools such as VCS and Modelsim.
• A thorough understanding of high-speed interfaces including PCIe, CXL, and NVMe.
• Hands-on experience with lab equipment like PCIe Exercisers and Analyzers.
• Expertise in developing system or IP prototypes using FPGAs.
• Strong capability in scripting languages including Tcl, Perl, Python.
• Knowledge of C/C++ is a plus.

Education Requirements

A Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.