Lead RTL Design Engineer

Role Summary

The Lead RTL Design Engineer will contribute to the development of PCIe technologies for use in various applications, focusing on the design and execution of RTL for new and existing PCIe solutions. This role requires in-depth knowledge of high-speed interfaces and collaboration across different engineering teams.

Experience Level

This position targets candidates with at least 8 years of experience in computer engineering or electrical engineering, particularly in roles involving digital design, verification, and high-speed interfaces.

Responsibilities

• Develop and productize next generation PCIe, CXL, and connectivity solutions.
• Engage in the full product development cycle, covering exploration, architecture, implementation, and validation.
• Create comprehensive testing plans for compliance and interoperability.
• Perform pre-silicon and post-silicon validation for new PCIe blocks.
• Handle tasks related to IP design, silicon bring-up, validation, and release.
• Collaborate with global teams to ensure project coherence and success.

Requirements

Candidates should possess strong knowledge in RTL coding, especially with Verilog and SystemVerilog, along with proficiency in RTL simulation tools such as VCS and Modelsim. Familiarity with high-speed interfaces like PCIe, CXL, and various protocols is critical. Experience with FPGA prototyping and scripting languages such as Tcl, Perl, and Python is desired. Knowledge of C/C++ would be beneficial.

Education Requirements

A Bachelor's or Master's degree in Computer Engineering or Electrical Engineering is required.