Lead MTS Physical Design/STA

Role Summary

The Lead Static Timing Analysis Engineer will be responsible for full chip-level static timing analysis for high-speed mixed-signal designs at Rambus in Bangalore. This position requires collaboration with various teams to ensure timing closure and design integrity.

Experience Level

10 – 12 years of experience, with at least 8 years specifically focused on Static Timing Analysis (STA) and synthesis.

Responsibilities

• Complete ownership of Static Timing Analysis at the full chip level for high-speed mixed signal design.
• Perform multi-mode multi-corner (MMMC) timing and power analysis using Primetime/Tempus.
• Handle DMSA/Tweaker ECO flows for PPA improvements.
• Generate manual timing fixes and ECOs for MCMM mode corners.
• Translate timing requirements into SDC constraints.
• Integrate blocks and analog IPs for full chip timing analysis.
• Utilize place and route methodologies and manage timing convergence.
• Communicate effectively with project leaders for schedules and risk management.
• Mentor new joiners on technical skills within the group.
• Provide design implementation inputs to the CAD/DA team.
• Collaborate with Logic design and Analog teams for input on physical design and STA.
• Work on scan aspects with the DFT team to ensure design quality.
• Continuously improve methodologies and productivity.

Requirements

Must possess detailed knowledge of constraints and signoff closure methodologies for STA and RTL2GDS flow. Experience in Tcl/Tk and PERL is a plus.

Education Requirements

A relevant degree in Electrical Engineering or a related field is expected. Advanced degrees may be advantageous.