Lead MTS Layout Design

Role Summary

This role involves leading the layout design process for chips within the MIC Design IDC team based in Bangalore. As the Lead MTS Layout Design, you'll report to the layout manager and will take ownership of the chip level collaterals, actively collaborating with designers to address layout challenges.

Experience Level

The position requires a seasoned professional who possesses a minimum of 8 years of relevant experience in electrical or electronic engineering, with a strong background in integrated circuit layout design.

Responsibilities

Your primary responsibilities in this role will include:

• Performing layout design of assigned blocks using Cadence Virtuoso XL/VXL features.
• Conducting layout verification checks such as LVS, DRC, Antenna, and Density using Calibre.
• Collaborating with cross-functional teams to resolve layout-related issues and applying standard layout practices.
• Addressing reliability issues, including EMIR and ESD/Latchup, while ensuring compliance with layout best practices.
• Engaging with Analog Designers globally to tackle complex design challenges.

Requirements

To be successful in this role, candidates should meet the following qualifications:

• Minimum of a Bachelor's degree in Electrical/Electronic Engineering or a related field.
• Extensive knowledge in layout design for various integrated circuit components, including transmitters, receivers, PLLs, and voltage regulators.
• Experience with modern semiconductor technology nodes, including 22nm, FINFET 16nm, 12nm, and 7nm.
• Sound understanding of device matching, signal shielding, and layout-dependent effects.
• Familiarity with scripting languages such as skill, Perl, or Tcl is preferred.
• A self-motivated team player with a drive for innovative problem-solving.