Role Summary
The verification team at Advanced Micro Devices (AMD) is seeking a Lead IP Verification Engineer to oversee and contribute to the verification of Network on Chip (NOC) intellectual properties (IPs) and subsystems. The role involves architecting and developing verification environments to ensure the functional correctness of complex digital designs.
Experience Level
Qualified candidates should have a minimum of 8 years of experience in the field of IP verification and digital design. A strong background in working with various verification methodologies and tools is essential.
Responsibilities
- Lead and plan verification efforts for complex digital design blocks, ensuring understanding of architecture and specifications.
- Collaborate with architects and design engineers to create comprehensive verification test plans.
- Design and architect testbenches using System Verilog and UVM for efficient verification processes.
- Develop and enhance constrained-random and directed verification environments, utilizing System Verilog Assertions (SVA) and formal verification tools.
- Debug tests in conjunction with design engineers to ensure functional correctness.
- Identify coverage measures and conduct coverage analysis to improve stimulus quality and achieve closure on metrics.
Requirements
- Strong proficiency in UVM, OVM, VMM, System Verilog, Verilog test benches, and simulation tools like Synopsys VCS and Cadence IES.
- Deep understanding of verification techniques, particularly assertion and coverage-driven verification.
- Experience in block level NOC verification, ASIC phases, and various digital protocols like AXI, DDR, and PCIe is advantageous.
- Familiarity with managing verification tools and understanding database management for regression management is beneficial.
- Knowledge of formal property checking tools is a plus.
Education Requirements
A Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering is required for this position.