Lead IP/SOC Verification

Role Summary

The Lead IP/SOC Verification role involves overseeing the design verification process for next-generation graphics programs. This position requires collaboration across various engineering teams to resolve verification needs effectively.

Experience Level

This position is suitable for experienced professionals with a strong background in IP and/or SOC verification, particularly those who have successfully overseen multiple ASIC projects from concept to production.

Responsibilities

• Collaborate with designers to develop features and verification plans.
• Lead the verification quality for GFXIP projects.
• Engage with IP and SOC teams to finalize verification strategies.
• Develop and drive quality in test plan specifications.
• Work with architects and engineers to assess complex features and their impact on SOC environments.
• Advance verification strategies and infrastructure improvements.
• Ensure pre and post silicon verification closure aligns with quality and schedules.
• Lead post-silicon verification activities, facilitating communication between various teams to enhance IP quality.
• Implement automated workflows within distributed computing environments.
• Support management in risk assessments regarding features and schedules.
• Drive excellence in execution by focusing on performance, schedule, cost, and quality metrics.
• Plan, execute, verify, and track new features at IP and SoC levels.
• Foster leadership aspirations progressively over time, moving towards a technical lead role.
• Initiate and implement improvements to existing processes for enhanced efficiency.

Requirements

Candidates should possess a robust understanding of technical leadership, including planning, execution, tracking, and delivery of programs. Strong experience with UVM, SystemVerilog, C/C++, and scripting languages is required, alongside familiarity with verification techniques such as assertion and metric-driven methods.

Education Requirements

A Bachelor’s degree is required, with a preference for candidates holding a Master's or PhD in Electrical or Computer Engineering.