Lead Digital Verification Engineer

Job Title

Lead Digital Verification Engineer

Role Summary

Join the IP verification team to verify digital RTL and develop reusable verification components and environments for high-performance physical IP supporting industry-standard protocols. Deliver verification flows, test plans, and coverage closure while collaborating with design and project teams globally.

Role is based in Montreal within the Design IP organization and requires cross-functional communication with digital, analog, and physical design teams.

Experience Level

Senior. Years of experience not specified.

Responsibilities

The primary responsibilities include:

• Plan and execute verification of digital RTL.
• Design and implement reusable verification components and UVM-based environments.
• Develop and execute test plans and stimuli to achieve functional and code coverage targets.
• Define, track, and close functional coverage and metrics-driven verification objectives.
• Implement SystemVerilog Assertions and integrate formal checks where applicable.
• Develop verification flows and automation to improve efficiency.
• Collaborate with design, physical, and project teams across locations and report development status.
• Work independently to meet project timelines and produce high-quality deliverables.

Requirements

Must-have skills and experience:

• Strong understanding of verification architecture and methodologies, including metric-driven verification.
• Familiarity with Universal Verification Methodology concepts and SystemVerilog Assertions.
• Understanding of digital design flow and fundamental logic principles.
• Ability to work independently and communicate technical status clearly in English.
• Willing to work full time in the Montreal, QC, Canada office; travel up to ~5% as required.

Nice-to-have:

• Hands-on SystemVerilog UVM coding experience.
• Experience with scripting languages such as Python, Perl, Ruby, Sed, or Awk for automation.
• Exposure to standard protocols (PCIe, USB, SATA, Ethernet, DisplayPort, HDMI).
• Exposure to formal verification, mixed-signal verification, Cadence tools, and low-power methodologies (CPF/UPF).

Education Requirements

Required: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. Preferred: Master of Science in EE/CPE/CS.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.