Lead DFT Engineer - MBIST

Job Title

Lead DFT Engineer - MBIST

Role Summary

Senior Design-for-Test (DFT) engineer responsible for architecting, implementing, and validating DFT solutions for complex SoCs with a focus on MBIST, scan insertion, ATPG and gate-level simulation. The role works closely with physical design (PnR) teams and silicon bring-up to ensure testability and design closure.

Experience Level

Senior — typically 10+ years of industry experience in DFT and semiconductor test engineering.

Responsibilities

Primary responsibilities include DFT architecture, verification, and support for silicon bring-up and manufacturing test.

• Define and implement DFT architecture: Scan, MBIST, and Test Access Mechanisms.
• Lead scan insertion and ATPG pattern generation and validation.
• Develop and integrate MBIST solutions for embedded memories (SRAM, MRAM, ROM).
• Perform RTL-level DFT verification and debug.
• Execute and debug gate-level simulations with SDF back-annotation.
• Validate scan patterns, MBIST controllers, and test protocols across functional/scan/mbist modes.
• Run redundancy analysis and manage repair flows, including Fuse/OTP programming and repair signature integration.
• Analyze failure logs, support post-silicon diagnostics and ATE debugging.
• Collaborate with PnR for scan chain stitching, reordering, and writing SDC for test timing closure.
• Support silicon bring-up and develop manufacturing test strategies.

Requirements

Must-have technical skills and hands-on experience required for the role.

• Must have: Extensive hands-on experience in JTAG, Scan, Memory BIST, and ATPG flows (10+ years recommended).
• Must have: Expertise with Tessent ATPG/MBIST tools (mandatory).
• Proficient in SystemVerilog and UVM-based verification environments.
• Experience with gate-level simulation, SDF back-annotation, and working with ATE patterns.
• Strong testbench development, simulation, and debug skills; post-silicon failure analysis and diagnostic experience.
• Proficient scripting and automation skills (Tcl, Python, Shell).
• Experience driving ATPG pattern coverage improvement and validating patterns on silicon.
• Nice to have: RTL development and functional verification experience; strong cross-functional communication skills.

Education Requirements

Bachelor's (BSEE) or Master's (MSEE) degree in Electrical Engineering.

About the Company

Company: GlobalFoundries

Headquarters: Saratoga Springs, New York, USA

GlobalFoundries is a leading contract manufacturer for the global semiconductor industry, with facilities in multiple countries, including the USA. The company develops a broad portfolio of semiconductor technologies and employs around 13,000 people worldwide. GlobalFoundries focuses on enhancing competitiveness in specialized application solutions and fostering innovation in mobile communications, consumer electronics, and automotive applications.