Lead Design Engineer

Job Title

Lead Design Engineer

Role Summary

Lead verification engineer responsible for defining and executing verification strategy, designing scalable testbenches, and providing technical sign-off for ASIC/SoC blocks. Works closely with design, architecture, emulation, and project teams to close verification gaps and resolve complex bugs.

Experience Level

Senior — typically 4–6 years of hands-on design verification (DV) experience in semiconductor/ASIC/SoC environments.

Responsibilities

Accountable for verification planning, execution, and final technical approval for assigned blocks or subsystems.

• Define verification strategy and methodology, typically UVM/SystemVerilog.
• Design scalable, reusable testbench architecture including BFMs, monitors, scoreboards, and checkers.
• Develop complex constrained-random testcases and sequences to achieve functional coverage goals.
• Perform root-cause analysis and lead debug with design engineers to drive fixes.
• Use formal verification tools to prove properties and find deep bugs beyond simulation.
• Monitor and analyze functional and code coverage; drive coverage closure activities.
• Oversee gate-level simulation to verify timing and reset behavior; define sign-off criteria.
• Mentor junior engineers and act as primary technical contact across cross-functional teams.
• Manage verification schedule, identify risks, and prioritize verification tasks to meet project deadlines.

Requirements

Must-have technical skills and experience for immediate contribution.

• 4–6 years of hands-on design verification experience in semiconductor/ASIC/SoC companies.
• Strong SystemVerilog and UVM experience; ability to implement advanced testbench architectures.
• Experience building BFMs, monitors, scoreboards, checkers, and complex verification environments.
• Skilled in constrained-random stimulus generation and functional coverage-driven verification.
• Practical experience with formal verification methods and interpreting results.
• Experience with gate-level simulation and verification of timing/reset behavior.
• Proven debugging and root-cause analysis skills; ability to collaborate effectively with design teams.
• Demonstrated mentorship and cross-functional communication; ability to drive sign-off decisions.
• Nice to have: emulation familiarity and scripting (e.g., Python) for automation and debug flows.

Education Requirements

B.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or a related technical field (as stated in the posting).

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.