Lead Design Engineer

Role Summary

The Lead Design Engineer at Cadence is responsible for developing test plans, tests, and verification infrastructure for complex IPs, subsystems, and SOCs. This role involves leading functional coverage verification closure and creating verification environments using UVM methodology or equivalent.

Experience Level

Mid-level, requiring 4-7 years of VLSI industry experience in verification.

Responsibilities

The main responsibilities include:

• Development of test plans and tests for complex IPs/sub-systems/SOCs.
• Creation of verification environments using UVM methodology or equivalent.
• Construction of reusable bus functional models, monitors, checkers, and scoreboards.
• Leading functional coverage verification closure.

Requirements

Must-have skills include:

• BTech/MTech in Engineering or equivalent relevant degree.
• 4-7 years of experience in VLSI industry verification.
• Expertise in SoC level verification and IP/subsystem validation.
• Proficiency in developing test bench/testbench components, test plans, and test cases.
• Strong knowledge of UVM and SystemVerilog (SV).
• Familiarity with protocols like UCIe, PCIe, DDR, USB, AMBA.
• Exceptional debugging and problem-solving abilities.
• Extensive experience in the verification cycle for complex SOCs.

Education Requirements

Required education includes BTech/MTech in Engineering or an equivalent relevant qualification.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.