Lead Design Engineer

Job Title

Lead Design Engineer

Role Summary

Lead pre- and post-silicon subsystem prototyping, validation, firmware and hardware design for high-speed SERDES test chips. Lead bring-up, debug, compliance and system characterization, and coordinate interop and customer debug activities.

Work within a hardware-focused team responsible for SERDES PHY, controllers, protocol and subsystem integration.

Experience Level

Senior — typically 5+ years of relevant experience. The posting specifies 5 years with a BTech or 1 year with an MTech, or equivalent professional experience.

Responsibilities

Primary responsibilities include:

• Lead pre-silicon emulation and verification using simulators (e.g., NCSIM, Palladium) and coordinate with verification teams.
• Design hardware and subsystem boards; own HW/SW infrastructure for projects.
• Prototype firmware and FPGA solutions for high-speed SERDES protocols (PCIe, CXL, UCIe, USB, Ethernet).
• Lead bring-up, debug, compliance testing and system-level characterization through to report release.
• Perform interop and customer debugging; deploy and debug solutions in customer environments.
• Mentor and manage a small team of engineers; coordinate cross-team efforts.

Requirements

Key qualifications. Items labeled "Must-have" are required; "Nice-to-have" are preferred.

• Must-have: Proven post-silicon PHY, systems interop and compliance testing experience, including at least one high-speed SERDES (PCIe, CXL, UCIe, Ethernet).
• Must-have: Demonstrated lab debug skills and experience with oscilloscopes, bit error rate testers, protocol exercisers and analyzers.
• Must-have: 2–3 years of management or mentoring experience leading small engineering teams.
• Must-have: Strong troubleshooting and system bring-up skills across hardware, firmware and FPGA platforms.
• Nice-to-have: Experience with PCIe/UCIe LTSSM states, FPGA design and schematic capture (1–2 years), and IP/SoC physical-layer electrical validation.
• Nice-to-have: Familiarity with Verilog for FPGA, Python and C/C++ for firmware and test automation.
• Nice-to-have: Experience leading system testing efforts for SERDES solutions and working directly with customers on interoperability.
• Good verbal and written communication skills.

Education Requirements

BE/B.Tech or ME/M.Tech (or equivalent degree). The posting also accepts equivalent practical experience in place of formal degrees.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.