Lead Debug/Trace/Profiling Design Engineer

Job Title

Lead Debug/Trace/Profiling Design Engineer

Role Summary

Lead hardware design engineer responsible for architecting, designing and delivering debug, trace and profiling IP for SiFive processor families. The role drives hardware generator-based implementations, integration into SiFive's Chisel/FIRRTL framework, verification, and documentation, and coordinates with architecture, software, performance, and verification teams.

This position may require background checks, verification of right-to-work, and export-control authorization where applicable.

Experience Level

Level: Senior. Requires 7+ years of industry experience leading and contributing to architecture, microarchitecture and RTL design for debug/trace/profiling hardware for high-performance processors.

Responsibilities

Primary responsibilities include design, integration, verification and documentation of debug/trace/profiling hardware and generators.

• Architect, design and implement debug, trace and profiling hardware and configurable RTL generators.
• Collaborate with architecture, performance, software and hardware teams on microarchitecture exploration and specifications.
• Integrate new designs into the Chisel/FIRRTL framework and improve generation/automation for docs, verification testbenches and software packaging.
• Perform initial sandbox verification and work with verification teams to create and execute detailed verification plans.
• Create and maintain clear documentation and participate in collaborative design reviews.
• Engage with customers, partners and tools vendors to align solutions and requirements when needed.

Requirements

Must-have technical skills, experience and behaviors are listed first; useful extras are noted as "Nice-to-have."

• Must-have: Deep knowledge of debug, trace and profiling architectures and concepts.
• Must-have: Experience with debug interfaces such as JTAG and cJTAG.
• Must-have: Strong understanding of CPU architectures, power management and SoC design.
• Must-have: Proven experience with debugging tools and profiling methods.
• Must-have: Proficiency in RTL design using Verilog, SystemVerilog, or VHDL.
• Must-have: Demonstrated leadership and 7+ years designing/debugging/validating debug/trace/profiling hardware for high-performance processors.
• Must-have: Ability to work effectively on cross-functional teams and produce high-quality documentation.
• Must-have: Familiarity with at least one object-oriented or functional programming language.
• Nice-to-have: Experience with Chisel/Scala, RISC-V architecture, and modern development tools (Git, Jira, Confluence).
• Nice-to-have: Experience building generator-based RTL flows, automated documentation/test generation, or engaging with standards bodies and tools vendors.

Education Requirements

MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline is listed as the expected education.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.