Lead DDR Verification Engineer

Job Title

Lead DDR Verification Engineer

Role Summary

The candidate will be responsible for maintaining and upgrading infrastructure and automation for RTL development and design-verification teams across multiple locations. Duties include managing regression trends, automating error reporting, and providing user support on various server farms.

Experience Level

Senior level; at least 7 years of relevant experience required.

Responsibilities

The candidate's key responsibilities will include:

• Maintaining and upgrading infrastructure for RTL development and design-verification.
• Managing and monitoring regression trends.
• Automating error and defect reporting.
• Supporting users across multiple server farms.

Requirements

Essential qualifications include:

• Extensive knowledge of Perl and Python.
• Experience with LSF or other batch-queuing systems.
• Familiarity with using REST API from Perl and Python.
• Knowledge of SQL and relational database engines.
• Basic web technologies including Apache, PHP, and Javascript.

Desirable skills:

• BS/MS in Electrical or Computer Engineering.
• Experience with Jenkins installation and management.
• Cloud deployment experience including AWS, Azure, and IBM Cloud.
• Experience with revision control systems like git.

Education Requirements

BS/MS in Electrical or Computer Engineering preferred.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.