Lead ASIC Design Engineer

Job Title

Lead ASIC Design Engineer

Role Summary

Serve as the Chip Lead for next-generation ASIC/SoC projects, owning top-level digital architecture, microarchitecture, and full-chip integration through foundry tape-out.

Lead and coordinate cross-disciplinary teams (logic design, physical design, verification, analog) to deliver silicon that meets power, performance, and area targets.

Experience Level

Senior — 12+ years of ASIC/SoC digital design experience with history of owning chip projects or serving as a design lead.

Responsibilities

Primary technical and delivery responsibilities for chip architecture, integration, and tape-out:

• Define top-level digital architecture and partition hard/soft IP blocks as the Chip Lead.
• Own end-to-end integration and tape-out sign-off, coordinating across teams to meet PPA targets.
• Align logic design, physical design, architecture, and verification efforts; establish timing budgets and CDC strategy.
• Author, optimize, and maintain synthesizable SystemVerilog/Verilog RTL for complex digital blocks and control logic.
• Drive synthesis and STA flows (Design Compiler/Genus, PrimeTime/Tempus) and execute static quality checks (lint, CDC, formal).
• Manage integration of internal analog macros, mixed-signal blocks, and third-party IP.
• Support initial silicon bring-up, lab debug, and collaborate with post-silicon validation and software teams.
• Provide mentorship, code reviews, and architectural guidance to mid-level and junior engineers.

Requirements

Must-have technical skills, experience, and eligibility:

• Must-have: Proven track record as a chip lead or design lead on ASIC/SoC projects.
• Must-have: Expert-level SystemVerilog/Verilog RTL design and microarchitecture skills.
• Must-have: Deep experience with front-end EDA tools for synthesis, STA, and CDC analysis (Synopsys/Cadence tool suites).
• Must-have: Demonstrated successful first-pass silicon tape-outs on modern process technologies.
• Must-have: Strong technical writing and verbal communication skills; able to produce authoritative architectural and design specifications.
• Must-have: Legal authorization to work in the United States.
• Nice-to-have: Experience with mixed-signal or high-speed PHY-adjacent architectures (SerDes, PCIe, DDR) or custom interconnects.
• Nice-to-have: Familiarity with DFT planning (scan insertion, ATPG, boundary scan).
• Nice-to-have: Scripting proficiency (Python, Tcl, Perl) to automate front-end flows.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.