Layout Engineer - DPG Layout

Job Title

Layout Engineer - DPG Layout

Role Summary

Execute block-level physical layout for analog, mixed-signal, and custom digital blocks and support full-chip integration for advanced CMOS processes. The role focuses on quality, manufacturability, verification closure, and timely delivery within the layout team.

Experience Level

Mid-level. Prefer candidates with 3+ years of experience in analog/custom layout design in advanced CMOS processes.

Responsibilities

Primary responsibilities include physical layout implementation, verification, and collaboration with cross-functional teams.

• Implement block-level layout for analog, mixed-signal, and custom digital circuits; ensure design intent and manufacturability.
• Perform layout verification activities including DRC, LVS, antenna checks, and yield/quality checks; own verification and closure for assigned blocks.
• Use semicustom tools to support custom/digital integration and accelerate ECOs and alignment during integration-level updates.
• Develop and apply automation (SKILL/Python/TCL) and AI-assisted methods to reduce manual effort and improve layout consistency.
• Collaborate with Design, Verification, CAD, and senior layout engineers; communicate status and risks clearly.
• Review and mentor junior engineers on layout techniques and best practices.

Requirements

Must-have technical skills and experience; desirable items noted below.

• 3+ years hands-on experience in analog/custom layout design for advanced CMOS processes.
• Proven experience with Cadence Virtuoso (VLE/VXL) and Calibre DRC/LVS, including ownership of verification and closure for assigned blocks.
• Experience laying out critical analog/mixed-signal blocks such as temperature sensors, PLLs, ADCs, DACs, LDOs, bandgaps, reference generators, and charge pumps.
• Strong understanding of analog layout fundamentals: matching and symmetry techniques, electromigration, latch-up, IR-drop, coupling, crosstalk, and parasitic effects.
• Ability to interpret design constraints and translate them into robust, manufacturable layouts that meet performance, power, and area targets.
• Hands-on experience developing or applying AI-driven automation or AI-assisted workflows for layout and verification tasks; scripting skills (SKILL, Python, TCL).
• Strong problem-solving skills for physical layout verification and debug; effective communication and teamwork.
• Nice-to-have: exposure to memory layout environments (DRAM, SRAM, CAM, OTP).

Education Requirements

B.Tech in Electronics, Electronics & Communication, or VLSI Engineering; M.Tech in VLSI Design, Microelectronics, or Electronics Engineering.

About the Employer

Micron is a global memory and storage company focused on high-performance DRAM, NAND, and related technologies. Micron is an equal-opportunity employer.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.