Layout Design Senior Engineer - IO SerDes

Role Overview

The role involves working as a Layout Design Senior Engineer focusing on IO SerDes at Synopsys. The position will require the individual to engage in layout designs for advanced semiconductor technologies, emphasizing high-performance devices.

Experience Level

This position is categorized as Level - Senior, suitable for candidates with significant industry experience and expertise in layout design.

Responsibilities

Key responsibilities include:

• Designing and implementing layout structures for high-speed IO interfaces.
• Collaborating with design and verification teams to resolve layout issues.
• Optimizing designs for manufacturability and performance.
• Performing layout verification using industry-standard tools.
• Providing leadership and mentorship to junior engineers in the team.

Requirements

Ideal candidates will possess the following qualifications:

• Extensive experience in layout design, specifically in IO SerDes.
• Proficiency in layout design tools such as Cadence or Synopsys.
• Strong understanding of DFM, DRC, and LVS processes.
• Excellent problem-solving and communication skills.
• A proven track record of successful project outcomes in a senior engineering role.

Education Requirements

A degree in Electrical Engineering or related field is required, with a preference for advanced degrees for senior roles.