Layout Design Engineer II (SerDes)

Job Title

Layout Design Engineer II (SerDes)

Role Summary

Responsible for transistor-level physical layout implementation of advanced analog and mixed-signal SerDes IP. The role is part of the SerDes Product Team in Cork and works with cross-functional engineering partners to deliver manufacturable, high-performance designs.

Experience Level

Mid-level (Layout Design Engineer II). Specific years of experience not specified.

Responsibilities

Key responsibilities include custom analog/mixed-signal layout and verification for high-speed interface blocks.

• Perform custom transistor-level layout for SerDes blocks (PLLs, CDR, TX/RX analog front-ends, CTLE/DFE equalisers, bandgap/bias circuits, high-speed clock distribution).
• Collaborate with analog and mixed-signal designers to meet performance requirements and optimise floorplanning, parasitic-sensitive routing, matching, and signal integrity.
• Support physical implementation tasks: floorplanning, device placement, routing, shielding/isolation, power planning, and EM/IR-aware layout practices.
• Run and debug physical verification flows including DRC, LVS, ERC, parasitic extraction, and post-layout verification support.
• Apply advanced layout techniques: common-centroid, interdigitation, symmetry constraints, guard rings, dummy fill, and matching-aware routing.
• Optimize layouts for area, yield, performance, reliability, and manufacturability.
• Work with cross-functional teams: Analog Design, Digital Implementation, Packaging, Signal Integrity, and Physical Verification.

Requirements

Must-have and desirable technical skills and experience.

• Must-have: Hands-on experience with CMOS SerDes or high-speed I/O IC transistor-level layout.
• Practical knowledge of custom layout methodologies and parasitic-aware design techniques.
• Ability to collaborate effectively across global teams; strong problem-solving and clear communication skills.
• Nice-to-have: Experience with PHY GDS implementation, PMA/PCS integration, and clock/power distribution.
• Familiarity with ASIC design flows, hierarchical physical design strategies, and deep sub-micron technology challenges.
• Exposure to EM/IR, low-power design considerations, crosstalk analysis, physical verification, and DFM.
• Tape-out experience on advanced technology nodes (for example 16nm, 10nm, 7nm, 5nm, 3nm).
• Scripting/automation skills (Tcl, Perl, Python) and prior use of Cadence tools (e.g., Virtuoso, PVS) are beneficial.

Education Requirements

Degree in Electronic Engineering, Microelectronics, Computer Engineering, or a related discipline, or equivalent industry experience. (The posting also accepts equivalent practical/industry experience in lieu of a degree.)

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.