IP Verification Lead (PLL & Mixed Signal Verification)

Role Summary

The IP Verification Lead will focus on the verification of complex Phase-Locked Loops (PLLs) delivered to AMD System on Chips (SoCs), utilizing advanced methodologies in a collaborative environment.

Experience Level

This position requires over 13 years of relevant experience in digital design and verification.

Responsibilities

• Develop and execute test plans for verifying IP features in RTL, Gatesim, and Analog Mixed Signal simulations.
• Create and maintain UVM-based verification testbenches and components from scratch.
• Ensure high-quality deliverables through rigorous regression testing.
• Achieve complete verification coverage through code-coverage, functional coverage, and assertions.
• Provide reviews and constructive feedback to design and architecture teams.

Requirements

• Expertise in System Verilog, UVM methodologies, and SVA.
• Strong problem-solving and debugging skills.
• Effective communication abilities for cross-site collaboration.
• Adept in digital design principles.
• Experience with UPF-based low power verification and leading a team is advantageous.
• Prior experience in PLL verification and analog-mixed methodologies is highly desirable.
• Familiarity with digital-analog co-simulation processes.

Education Requirements

A Bachelor’s or Master’s degree in Electronics or Electrical Engineering is mandatory.