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IC Design Engineer

Broadcom
April 30, 2026
Full-time
On-site
San Jose, California, United States
$127,100 - $203,400 USD yearly
Physical Design Jobs, Level - Senior
IC Design Engineer

Job Title

IC Design Engineer

Role Summary

Member of the Mixed-Signal ASIC Implementation team responsible for physical implementation of mixed-signal and digital ASICs across consumer and satellite products.

Work includes floorplanning, power and clock planning, physical verification, timing closure, and collaboration with design, IP, synthesis/STA, and library teams.

Experience Level

Senior — position expects an experienced engineer (guidance provided in Education Requirements: typically 10–12+ years of relevant industry experience).

Responsibilities

Primary responsibilities include full-chip and block-level physical implementation and delivery for high-volume and specialty ASIC projects.

  • Lead physical implementation for chips across nodes from ultra-low-power 40nm to 7nm, including block and top-level implementation.
  • Floorplanning for multi-power-domain designs, power-grid planning, block shaping, and clock-tree implementation.
  • Coordinate with design, IP, library, synthesis/STA owners, and RTL teams to meet physical and power-intent requirements.
  • Perform physical verification at block and chip level and resolve issues.
  • Conduct static and dynamic IR-drop analysis and signal/power EM checks.
  • Develop and improve physical design and timing-closure methodologies and flows.
  • Integrate analog blocks, ESD/IO pad ring considerations, and work with packaging types (flip-chip, WLCSP) where applicable.

Requirements

Key technical skills and hands-on tool experience required or strongly preferred.

  • Extensive hands-on experience with Cadence Innovus (essential) and physical implementation flows.
  • Experience with verification and signoff tools such as Calibre; knowledge of timing closure, Formality, LEC is expected.
  • Multiple tapeouts experience and proven delivery on ASIC projects.
  • TCL scripting is required; Python is a plus.
  • Experience collaborating with synthesis and STA teams on physical implementation and power intent.
  • Knowledge of ESD, IO pad ring, analog integration, and exposure to package types (flip-chip, WLCSP) is a plus.
  • Familiarity with static/dynamic IR drop and EM analysis.
  • Knowledge or experience with AI tools is preferable.

Education Requirements

BS in Electrical Engineering plus ~12 years of relevant experience, or MS in Electrical Engineering plus ~10 years of relevant experience. Fields referenced: Electrical/Electrical Engineering. (No other degrees or "equivalent experience" language specified in the posting.)


About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.

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Date Posted: 2026-04-28