HSIO DFT Lead Verification Engineer

Role Summary

The HSIO DFT Lead Verification Engineer at AMD will contribute as a key member of the design verification team focused on high-speed I/O technologies. This role centers around enhancing the quality and effectiveness of DFT verification processes, particularly involving PCIe, UCIe, and Chiplet interconnect IPs.

Experience Level

Candidates should have advanced expertise in digital design and verification, making them suitable for a senior-level position. Experience with related technologies and methodologies is essential.

Responsibilities

• Design verification of PCIe, UCIe, Chiplet Interconnect IPs for Analog/HSIO DFT features.
• Develop testbench components for the next generation of NBIO IPs.
• Estimate time for writing new feature tests and modifying the test environment.
• Maintain and enhance test libraries for IP level testing.
• Conduct test coverage analysis and cost reduction studies.
• Train and mentor junior engineers in DV execution.
• Support SoC and Post-Si teams to ensure robust bring-up and improve yield learning.

Requirements

Must possess strong analytical and problem-solving skills, with a collaborative mindset for working with teams across different locations. Communication proficiency in a team environment is critical.

Education Requirements

A Bachelor’s or Master’s degree in a related discipline is required.