High-Speed RTL Design Engineer

Job Title

High-Speed RTL Design Engineer

Role Summary

Design and implement timing-critical RTL blocks for high-speed semiconductor products. Work within an RTL design team to deliver clean, synthesis-ready logic that meets timing, power and functional requirements and integrates into larger subsystems.

Collaborate with verification, physical design and system teams to support integration, timing closure and production-ready documentation at the Bengaluru site.

Experience Level

Mid-level. Years of experience not specified.

Responsibilities

Accountable for RTL design, integration and support activities across the module lifecycle.

• Design and implement timing‑critical RTL blocks: control/sequencing FSMs, power‑up/shutdown and mode‑transition logic, register banks, configuration logic, and telemetry datapaths.
• Write nanometer‑process‑aware RTL that is robust to tight setup/hold margins, clock skew, multi‑cycle/false‑path constraints and PVT variation.
• Implement and review clock‑domain crossings (CDC), reset and initialization logic, and power‑aware mode behavior.
• Integrate RTL blocks into larger subsystems, resolve port/clock/reset/mode interaction issues, and debug with simulations and tool feedback.
• Support verification and timing closure by clarifying design intent, fixing RTL issues found in verification, and refining logic to address synthesis/PNR timing problems under guidance.
• Participate in RTL and design reviews and maintain clear block documentation describing functionality, assumptions and limitations.

Requirements

Must-have technical skills and practical experience.

• Strong proficiency in SystemVerilog/Verilog RTL coding and FSM implementation.
• Hands-on experience with reset synchronization, clock‑domain crossing concepts and timing‑critical control logic.
• Solid understanding of setup/hold timing fundamentals, critical‑path sensitivity and multi‑mode behavior.
• Familiarity with RTL lint, CDC checks, synthesis flows and basic static timing analysis (STA) reports.
• Knowledge of DFT‑friendly RTL practices, UPF and LEC; ability to debug issues during RTL sign‑off or late integration stages.
• Effective independent contributor who raises risks early, documents decisions, and incorporates review feedback.

Nice-to-have:

• Experience with PMICs, mixed‑signal SoCs or companion ICs.
• Exposure to industry‑standard specifications and mixed‑signal interactions.
• Basic scripting skills (Python, Tcl) for automation and integration tasks.

Education Requirements

Not specified.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.