High Speed IO Validation Engineer

Job Title

High Speed IO Validation Engineer

Role Summary

Join the Silicon Co-Design Group to own characterization and qualification of high-speed I/Os (PCIe, NVLink, NVLink-C2C, UCIe, USB, UFS, Ethernet) across NVIDIA GPUs, CPUs, and SoCs. Work spans silicon die through package and board, firmware, and drivers to ensure link margin, BER, and performance at system scale.

Experience Level

Mid-level - typically requires 3+ years of post-silicon HSIO validation, characterization, or closely related experience.

Responsibilities

Validate and characterize high-speed IO across silicon and platform boundaries; design tests and drive debug to ensure product readiness.

• Own end-to-end characterization and validation of HSIO subsystems from die to board for GPUs, SoCs, and CPUs.
• Develop and execute validation test plans: bring-up, corner qualification, stress, DOE across PVT, board, cable/connector, thermal, and firmware variables.
• Drive power characterization and optimization under workload-representative stimuli; analyze trade-offs across V/F, lane configuration, and protocol state.
• Perform systematic root-cause analysis for complex HSIO issues, isolating contributions from silicon, package, board, firmware, driver, and system.
• Convert rack-observed failures into reproducible silicon/board experiments and feed findings into design, firmware, and binning decisions.
• Assess manufacturing and yield implications of HSIO margin distributions and recommend mitigation strategies.
• Improve validation methodologies, automation frameworks, and margin-tracking infrastructure to increase coverage and efficiency.

Requirements

Must-have technical skills and experience for successful performance in this role.

• 3+ years of post-silicon HSIO validation, characterization, or closely related experience.
• Deep understanding of high-speed serial link protocols (PCIe Gen5+, NVLink, NVLink-C2C, UCIe, CXL) and SERDES architecture: link training, equalization, electrical characterization.
• Strong signal integrity (SI) and power integrity (PI) fundamentals: S-parameters, eye diagrams, channel margin, crosstalk, return loss, PDN noise, and jitter decomposition.
• Validation experience across silicon and platform boundaries (interposer/substrate, board) and translating rack/environment effects into silicon/board characterization.
• Hands-on experience with lab instrumentation (oscilloscopes, BERTs, VNAs, protocol/logic analyzers, TDR) and DOE/shmoo/margin-trending techniques.
• Python-based test automation and experience driving cross-functional debug with chip, package, board, firmware, driver, and system teams.

Nice-to-have:

• Experience with PCIe Gen5/Gen6 or NVLink validation on production silicon: link training, equalization tuning, BER margining, or compliance debug.
• SERDES, mixed-signal, or analog circuit design experience to support Sim-to-Si correlation and hypothesis-driven debug.
• Proven ability to map rack-environment conditions (thermal, connector reliability, neighbor noise) into silicon/board characterization.
• Familiarity with AI productivity tools (e.g., Claude, Copilot) for log triage, regression analysis, scripting, and reporting.

Education Requirements

BS or MS in Electrical Engineering or Computer Engineering (or equivalent practical experience).

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.