HDL Design/Verification Engineer (FPGA Simulation)

Role Summary

The HDL Design/Verification Engineer will design, develop, and enhance the simulation capabilities within Lattice Radiant, Lattice Semiconductor's official FPGA design tool, collaborating with hardware developers and QA teams.

Experience Level

5+ years of industrial experience in a similar field.

Responsibilities

Key responsibilities include enabling and supporting simulation workflows for Verilog, VHDL, and SystemVerilog across various Lattice FPGA families, diagnosing and resolving simulation issues, validating simulation features, contributing to automation scripts and testbench generation tools, and maintaining simulation documentation.

Requirements

Candidates should possess a Bachelor’s or Master’s degree in Electronics Engineering or a related field, solid experience with HDLs and simulation tools, understanding of HDL simulation concepts, experience in EDA tool development, and familiarity with Lattice Radiant Software. Strong analysis, debugging capabilities, and excellent communication skills are preferred.

Education Requirements

Bachelor’s or Master’s degree in Electronics Engineering, or related field.