HBM Design Verification Engineer - Principal

Synopsys is a leader in advanced chip design and software security technologies.

Role Summary

The Principal HBM Design Verification Engineer will develop verification strategies and plans for ASIC/SoC projects, build testbench architecture, and serve as a technical expert within the team.

Experience Level

10–15+ years of relevant experience in design verification.

Responsibilities

• Develop verification strategies and plans for ASIC/SoC projects.
• Define and implement testbench architecture and methodologies.
• Build testbench infrastructure and verification components.
• Create verification item lists, coverage models, and checkers.
• Provide clear, metric-driven reports on verification progress.
• Break down tasks, develop schedules, and manage deliverables.
• Lead and coordinate design review meetings.
• Serve as a technical expert and mentor within the team.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering (BSEE/MSEE).
• Extensive hands-on experience creating test environments from functional specifications using UVM/VMM/OVM.
• Proven expertise in constraint random verification, coverage closure, and failure analysis.
• Proficiency in SystemVerilog, UVM, and object-oriented verification methodologies.
• Experience with Verilog/SystemVerilog coding and simulation tools.
• Solid understanding of SoC/ASIC design flows and backend processes.
• Knowledge of one or more interface protocols: DDR, PCIe, AMBA (AMBA2, AXI, CHI), SD, eMMC, Ethernet, USB, MIPI.
• Experience working in Unix environments.
• Strong English communication skills, both written and verbal.
• Ability to work independently, drive innovation, and solve complex problems.
• Strong team player with excellent interpersonal skills.

Education Requirements

Bachelor’s or Master’s degree in Electrical Engineering (BSEE/MSEE).