Hardware Design Engineer - Graphics Silicon Implementation

Job Title

Hardware Design Engineer - Graphics Silicon Implementation

Role Summary

Implement and integrate Adreno GPU RTL into the ASIC implementation flow, from RTL integration through physical design. Work closely with graphics microarchitecture, verification, SOC, DFT and physical design teams to deliver production-ready GPU cores.

Focus areas include RTL integration and transformation, synthesis and timing closure, formal/netlist checks, ECOs, and front-end methodology improvements.

Experience Level

Mid-level - generally 0–5 years of relevant industry experience.

Responsibilities

Primary duties and deliverables for the role.

• Integrate and partition RTL; perform RTL transformations and prepare design for synthesis and implementation.
• Ensure implementation readiness using RTL lint, custom checks, CDC/CDN analysis, and unit-level synthesis checks.
• Run synthesis and static timing analysis; support timing closure and constraint development.
• Perform formal verification and netlist equivalence checks between RTL and netlist.
• Develop and execute ECOs for functional and timing fixes; verify ECO correctness.
• Package, qualify and deliver front-end design collateral to downstream teams.
• Collaborate with architecture, design, DV, SOC integration, DFT and implementation teams across sites.
• Improve front-end integration processes and develop methodology automation to increase delivery quality and efficiency.
• Manage tradeoffs and design goals in power, performance and area (PPA).

Requirements

Must-have skills and tools required to be productive from day one. Preferred skills that improve effectiveness are listed separately.

Must-have:

• Proficiency in Verilog and/or SystemVerilog for digital/RTL design and integration.
• Practical knowledge of RTL integration, partitioning, and clock domain crossing checks.
• Familiarity with synthesis, static timing analysis (STA), timing constraints, and timing closure workflow.
• Experience with formal verification and RTL/netlist equivalence checking.
• Exposure to Synopsys Design Compiler, Synopsys PrimeTime, and Conformal/LEC/Formality or equivalent tools.
• Experience using version control systems and basic scripting/automation workflows.

Nice-to-have:

• UNIX environment and scripting skills (Perl, TCL, shell).
• Experience with UPF/CPF power intent, CDC/RDC analysis, PPA optimization techniques, and physical design flows.
• Strong analytical, interpersonal skills and ability to work independently in a multi-site team.

Education Requirements

Required: Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field plus 4+ years relevant work experience; OR Master's degree in those fields plus 3+ years relevant experience; OR PhD in those fields plus 2+ years relevant experience.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.