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Front-End Implementation Engineer (Staff) - Timing & Synthesis

Qualcomm
October 8, 2026
Full-time
On-site
Cork, Ireland
Physical Design Jobs, Level - Senior

Job Title

Front-End Implementation Engineer (Staff) - Timing & Synthesis

Role Summary

Work on timing-constraint development, physical synthesis, formal verification and functional ECOs to bridge RTL and physical design for Snapdragon SoCs at 4nm and below.

Member of the Implementation team in Cork, responsible for driving and executing implementation flow across core and chip-level design phases.

Experience Level

Senior (Staff). Typical experience expected: approximately 5+ years in ASIC implementation, timing closure, or related physical design roles; posting indicates candidates with 5–10 years are typical.

Responsibilities

Day-to-day responsibilities include capture and delivery of timing and implementation artifacts, automation, and cross-team integration.

  • Create and maintain top-level timing constraints for large SoCs.
  • Perform physical synthesis and drive timing closure using STA methodologies.
  • Implement functional and timing ECOs to resolve RTL/physical mismatches.
  • Develop and maintain TCL and scripting for Synopsys CAD flows (TCL/Python/Perl).
  • Support formal verification and UPF/low-power checks as part of signoff.
  • Collaborate with RTL designers, physical design, DFT and validation teams to meet power, performance, and area targets.
  • Apply Design-for-Test concepts during implementation and handoff.

Requirements

Must-have technical skills and experience required to perform the role.

  • Proven experience in timing constraint development for large, complex SoC designs.
  • Strong skills in TCL for Synopsys tools and scripting (Python/Perl) for CAD automation.
  • Hands-on experience with physical synthesis and static timing analysis (STA) for timing closure.
  • Experience with formal verification methodologies and implementing functional/timing ECOs.
  • Familiarity with UPF and low-power verification checks.
  • Verilog RTL knowledge sufficient to diagnose RTL/implementation issues.
  • DFT implementation experience and understanding of test concepts.
  • Ability to work in cross-functional teams and drive implementation milestones.

Education Requirements

Bachelor's, Master’s or PhD in Science, Engineering, Electronics, Computer Engineering, Computer Science or related technical field; the posting accepts equivalent practical experience. Posting examples: Bachelor’s +4+ years, Master’s +3+ years, PhD +2+ years; other statements reference Masters in Electronics/Computer Engineering with ~5 years or candidates with 5–10 years’ experience.


About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.

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Date Posted: 2026-10-08