Front End ASIC RTL/Logic Senior Design Engineer

Role Summary

The Front End ASIC RTL/Logic Senior Design Engineer will lead the design of high-speed digital circuits, focusing on next-generation input/output technology in advanced nodes. The role involves collaboration with different teams to ensure comprehensive design implementation and validation.

Experience Level

Senior level with a minimum of 10 years of experience in ASIC frontend design.

Responsibilities

Key responsibilities include:

• Leading the definition and implementation of micro-architecture, RTL, linting, and synthesis for high-speed digital designs.
• Collaborating with verification and back-end teams for design validation and timing closure.
• Providing post-silicon debug and characterization support for designs.

Requirements

Must-have skills and qualifications:

• BS/MS or PhD in Electronics Engineering.
• Experience in ASIC frontend development with a minimum of 10 years.
• Strong communication, leadership, and analytical skills.
• Proficient in RTL coding using HDL and familiar with logic simulation and debugging tools.
• Knowledge of tools such as Spyglass, Synthesis, STA (PT), UPF, UVM, Spice, and DFT.
• Desirable: Scripting knowledge.

Education Requirements

BS/MS or PhD in Electronics Engineering is required.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.