Job Title
FPGA / VLSI Engineer
Role Summary
Design and validate digital hardware for ASIC/SoC platforms used in advanced communication systems, with emphasis on RTL design, FPGA prototyping, and system integration. Work closely with verification, ASIC, and software teams to deliver timing- and power-aware implementations.
This is an onsite position based in the Saratoga, CA office supporting LEO satellite communication systems.
Experience Level
Mid-level. The posting does not specify exact years of experience; the role expects independent handling of well-defined design blocks.
Responsibilities
Key responsibilities include design, prototyping, verification, and integration of digital subsystems.
- Design and implement RTL using SystemVerilog with attention to timing, power, and area.
- Perform FPGA prototyping, validation, and hardware bring-up for digital designs.
- Develop and execute simulation and debugging strategies at block and subsystem levels.
- Contribute to SoC-level integration, interfacing with processors, memory, and peripherals.
- Analyze and resolve timing issues, including setup/hold violations and basic clock domain crossing concerns.
- Collaborate with verification, ASIC, and software teams to ensure functional correctness and performance.
- Participate in design reviews and promote design quality and best practices.
Requirements
Must-have technical skills and work-authorization requirements; preferred skills listed separately.
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Must-have: Strong experience writing synthesizable SystemVerilog/Verilog and producing clean, timing-aware RTL.
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Must-have: Proven experience with FPGA development flows including synthesis, implementation, validation, and hardware bring-up.
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Must-have: Solid understanding of digital design fundamentals and timing analysis (STA), and experience resolving setup/hold issues and CDC concerns.
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Must-have: Experience targeting ASIC/SoC platforms and performing SoC-level integration.
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Must-have: Authorized to work in the United States; the company cannot provide employment sponsorship for this role.
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Nice-to-have: Experience with SoC FPGA platforms (Xilinx Zynq, Intel SoC FPGA) and familiarity with AXI/AHB or similar bus protocols.
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Nice-to-have: Exposure to ASIC design flow (synthesis, STA), high-speed interfaces (PCIe, Ethernet), and communications systems (e.g., 5G PHY/MAC concepts).
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Nice-to-have: Experience with LEO satellite component development or in-orbit activities.
Education Requirements
Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related technical field.
About the Company
Company: PDDN
PDDN is an engineering services firm specializing in ASIC and SoC verification, with expertise in ARM IPs (e.g., Cortex-A, Mali), UVM/SystemVerilog-based verification, formal methods, coverage analysis, and CI/CD-enabled hardware verification workflows.

Date Posted: 2026-05-21