Job Title
FPGA Engineer β Verilog, SystemVerilog & Embedded C
Role Summary
Work on architecture, design, implementation, and verification of FPGA-based Electronic Safe and Arm Devices for DOD weapon systems. The role combines FPGA design, embedded firmware, and algorithm development to deliver reliable, safety-critical hardware and software.
Experience Level
Mid-level. Specific years of experience were not stated.
Responsibilities
Primary duties include hardware/firmware design, requirement analysis, and product verification.
- Design, implement, and verify FPGA logic using Verilog and SystemVerilog.
- Develop and maintain embedded firmware in C for target platforms.
- Use C# and related tooling for test automation, data processing, or support utilities.
- Translate system requirements into hardware and software specifications and architectures.
- Debug, simulate, and validate designs in lab and simulation environments to ensure product quality.
- Collaborate with cross-functional teams to integrate FPGA and embedded components into the product.
- Follow development methodologies and maintain documentation for design and verification activities.
Requirements
Key technical skills and experience. Items labeled as "must-have" are mandatory when possible to infer; others are desirable.
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Must-have: Practical experience with FPGA design using Verilog and SystemVerilog.
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Must-have: Embedded firmware development in C and familiarity with embedded toolchains.
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Must-have: Proficiency in C# and C for development or test automation tasks.
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Must-have: Strong digital design and algorithm development skills; experience with debugging and verification (simulation and lab).
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Nice-to-have: Experience with FPGA toolchains (e.g., Vivado, ModelSim), hardware interfaces (SPI, I2C, UART) or embedded RTOS.
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Nice-to-have: Prior work on safety-critical or defense-related systems.
Education Requirements
Not specified.
About the Company
Company: Retym Israel
Technology company hiring VLSI/ASIC digital design engineers for communication systems and SoC/IP development. Work includes RTL design, verification, synthesis, timing closure, and silicon bring-up.

Date Posted: 2026-07-09