FPGA Engineer

Job Title

FPGA Engineer

Role Summary

Responsible for planning and executing verification activities for complex FPGA designs. The role collaborates with design engineers to verify functionality, performance, and reliability and to drive verification strategy and coverage closure.

Experience Level

Mid-level — requires 3+ years of FPGA verification experience.

Responsibilities

Primary responsibilities include developing verification environments, executing test plans, and working with designers to resolve issues.

• Develop and execute FPGA verification plans and strategies.
• Design, build, and maintain UVM/SystemVerilog testbenches.
• Write and debug test cases that exercise functionality and corner cases.
• Perform code and functional coverage analysis and drive coverage closure.
• Investigate and debug issues in coordination with design engineers.
• Document verification results and participate in design reviews.

Requirements

Must-have technical skills and experience for the role.

• Strong FPGA design and architecture knowledge.
• Proficiency in SystemVerilog and UVM.
• Experience with simulation and verification tools such as QuestaSim or Synopsys VCS.
• Proven debugging and problem-solving skills for RTL and verification environments.
• Experience with scripting (Python or Perl) and familiarity with HDLs (VHDL or Verilog).
• 3+ years of FPGA verification experience (already noted in Experience Level).
• Nice-to-have: additional verification tool experience or advanced verification methodology knowledge.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.

About the Company

Company: UST

Headquarters: Aliso Viejo, CA, United States

Global digital technology and transformation company providing IT services, software engineering, and consulting to enterprises across industries, including cloud, digital engineering, and business process solutions.