FPGA/ASIC Verification Engineer

Job Title

FPGA/ASIC Verification Engineer

Role Summary

Verify FPGA designs and embedded firmware for tactical radio communication systems used by military and first responders. Work on a cross-functional engineering team to plan, implement, and close verification activities using SystemVerilog and UVM-based testbenches.

Experience Level

Mid-level. Typical candidate has several years of FPGA/ASIC verification experience (the posting indicates around 6 years of relevant experience as a guideline).

Responsibilities

Primary responsibilities involve planning and executing functional verification for FPGA designs, reporting coverage, and collaborating with design and systems teams.

• Develop and execute verification plans from requirements through closure.
• Create self-checking SystemVerilog testbenches within a UVM framework.
• Implement Agents, Test sequences, Cover groups, Predictors, and Scoreboards.
• Write randomized and directed tests to achieve functional coverage goals and provide actionable feedback to the design team.
• Verify FPGA/ASIC embedded system solutions and validate implementations against specifications.
• Work with cross-functional teams to define and verify product and design requirements.
• Prepare and present technical briefings, design and implementation reviews, and status reports to internal and external stakeholders.
• Maintain documentation and test artifacts required for verification closure and audits.
• Ability to obtain and maintain U.S. security clearance.

Requirements

Must-have technical skills and experience for successful performance in this role.

• Must-have: Proven proficiency in FPGA/ASIC verification using SystemVerilog and UVM/OVM methodologies.
• Must-have: Experience developing self-checking testbenches, functional coverage, and using advanced verification tools to report coverage.
• Must-have: Hands-on experience debugging FPGA firmware and related hardware integration issues.
• Must-have: Familiarity with industry-standard interfaces such as Ethernet, AXI, and SPI.
• Must-have: Experience with scripting for verification flows (Bash, Perl, Python, Tcl) and working in Linux environments.
• Nice-to-have: Experience with Mentor Graphics verification tools and FPGA/ASIC RTL design.
• Nice-to-have: Knowledge of Ethernet packet processing and cryptographic algorithms for embedded communication systems.
• Nice-to-have: Proficiency in object-oriented programming (C++, Java) and use of advanced functional verification tooling.
• Nice-to-have: Strong technical writing and communication skills; ability to present technical concepts clearly.

Education Requirements

Posting specifies: Bachelor's degree plus a minimum of 6 years of relevant experience; or a graduate degree with a minimum of 4 years of related experience; or in lieu of a degree, a minimum of 10 years of related experience. No specific fields of study were listed.

About the Company

Company: Retym Israel

Technology company hiring VLSI/ASIC digital design engineers for communication systems and SoC/IP development. Work includes RTL design, verification, synthesis, timing closure, and silicon bring-up.