Foundational IP Integration QA Lead

Role Overview

The Foundational IP Integration QA Lead will oversee the QA progress for Foundational IPs at Intel, focusing on enhancing integration testing across various development nodes. This role is crucial in ensuring that quality standards are maintained and continuously improved in our processes.

Experience Requirements

This position is intended for experienced professionals, requiring a minimum of 8 years in sectors such as SoC, analog, IP, or ASIC design alongside a relevant Bachelor’s degree. Master’s or Ph.D. qualifications will further enhance a candidate’s profile.

Key Responsibilities

As the Foundational IP Integration QA Lead, your primary duties will include:

• Tracking FIP platform and reference flow deliveries alongside QA requirements.
• Reviewing and improving FIP integration QA measures.
• Identifying best practices in QA automation and collaborating across design teams.
• Overseeing Full Chip Reference Design Development as a Timing Owner.
• Documenting QA progress and outcomes for all FIP releases.
• Fostering collaboration with internal teams and EDA vendors.

Essential Qualifications

Applicants should possess proficiency in design methodologies, including synthesis and physical design flow. Skills in static timing analysis, Unix/Linux, and experience with the full RTL to GDS design cycle are necessary. Familiarity with programming/scripting languages such as PERL and TCL is advantageous.

Education Requirements

A Bachelor of Science in Electronic, Electrical, or Computer Engineering, or equivalent is necessary. Advanced degrees will be considered beneficial.