Formal Verification Engineer

Job Title

Formal Verification Engineer

Role Summary

The Formal Verification Engineer will apply formal methods to exhaustively verify interconnect fabric, protocol bridges, and link-layer logic for silicon chassis designs. The role owns end-to-end formal verification from property specification through proof convergence across multiple protocol domains.

The engineer will work closely with architecture, RTL design, physical design, and software teams, contribute across discipline boundaries, and use AI-assisted workflows as part of the verification process.

Experience Level

Mid-level to Senior; 4–13 years of hands-on Formal Verification experience is preferred.

Responsibilities

Primary responsibilities include defining and executing formal verification plans, proving properties, and collaborating with cross-functional teams to close verification gaps.

• Develop and execute comprehensive formal verification test and coverage plans, defining scope, strategy, and techniques.
• Create abstraction models and apply abstraction techniques to enable proof convergence.
• Generate and validate formal proofs and resolve failing tests through corrective measures.
• Collaborate with architecture, RTL design, and physical design teams on complex architectural and microarchitectural verification.
• Maintain and enhance formal verification infrastructure, tools, and methodologies.
• Model problems using architecture modeling techniques to verify protocols and architectures.
• Use tools to address BDD complexity and optimize data paths for convergence.
• Document test plans, track verification progress, and drive technical reviews with cross-functional teams.

Requirements

Must-have technical skills and competencies for successful execution of the role.

Must-have:

• Proficiency in formal verification tools and methodologies, including model checking and equivalence checking.
• Strong knowledge of SystemVerilog, Verilog, and logic/microarchitecture fundamentals.
• Experience with abstraction modeling, simulation techniques, and convergence strategies.
• Familiarity with Binary Decision Diagrams (BDD) and Data Flow Graphs (DFG).
• Hands-on coding ability to implement verification infrastructure and scripts.
• Ability to mentor junior engineers and work across discipline boundaries.
• Track record of delivering against schedule and quality goals.

Nice-to-have:

• Experience verifying interconnect fabrics, protocol bridges, or link-layer logic.
• Experience with AI-assisted verification workflows.
• Strong technical documentation and cross-team communication skills.
• Proven problem-solving skills for complex architectural verification challenges.

Education Requirements

Bachelor's or Master's degree (BS/MS) in Electrical Engineering, Computer Science, or a related technical discipline. The posting specifies 4–13 years of hands-on formal verification experience.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.