Fellow Silicon Design Engineer

Role Summary

As a Fellow Silicon Design Engineer at Advanced Micro Devices, you will take the lead in defining the verification architecture and methodologies for high-speed interface PHY IP designs. This role involves shaping complex UVM testbench architectures and driving innovations in verification methodologies to ensure scalable and high-quality verification outcomes.

Experience Level

The position requires a minimum of 20 years of experience in ASIC/IP verification, with substantial expertise in high-speed interface protocols such as DDR, LPDDR, USB, and PCIe.

Responsibilities

• Architect & Own Verification Strategy: Lead the development of verification architecture for PHY IP and subsystems, ensuring alignment of test strategies and quality metrics.
• Advanced Testbench Leadership: Create reusable UVM-based environments and implement scalable verification infrastructure.
• HW/SW Co-verification: Develop flows integrating firmware with RTL; utilize virtual platforms for early software validation.
• AI-Driven Improvements: Implement ML/AI techniques for enhancing verification processes and predictive analytics for coverage.
• Methodology Innovation: Innovate coverage models and integrate formal and power-aware checks into verification pipelines.
• Cross-Functional Leadership: Collaborate with global teams to align design specifications and facilitate clear verification plans.
• Quality Metrics: Set and enforce rigorous quality KPIs and sign-off criteria for successful tape-outs.
• External Representation: Represent AMD in industry forums and contribute to verification technology standards.

Requirements

Candidates should possess deep knowledge in verification methodologies, including SystemVerilog and UVM, experience with HW/SW co-verification practices, and familiarity with AI/ML applications in verification. A proven track record of developing methodologies across multiple programs and effective cross-site team leadership is essential.