Experienced DFT ATPG Engineer

Job Title

Experienced DFT ATPG Engineer

Role Summary

The DFT ATPG Engineer designs and integrates design-for-test (DFT) features into RTL and structural code, generates test content for manufacturing, and supports test and debug through silicon bring-up and production. The role works within an IP/block team and with SoC, post-silicon, and manufacturing teams to ensure DFT features meet performance, timing, coverage, and production goals.

Experience Level

Mid-level — typical practical experience expectations vary by degree: MS-level candidates commonly have 1+ years of relevant DFT experience; BS-level candidates commonly have 3+ years. See Education Requirements for degree guidance.

Responsibilities

Primary responsibilities focus on implementing DFT features, producing test content, and resolving design and verification issues to support production readiness.

• Develop RTL and structural code to integrate DFT features (SCAN, MBIST, BSCAN, TAP, processor monitors, in-system test/BIST).
• Create and deliver test content and high-volume manufacturing (HVM) patterns for automatic test equipment (ATE) to support bring-up and ramp to production.
• Apply DFT strategies and tools to meet power, performance, area, timing, test coverage, defect-per-million (DPM), and test-time/vector memory targets.
• Review and drive verification of DFT designs; debug and resolve failing RTL tests and verification issues.
• Integrate DFT blocks into functional IP and SoC and support SoC customers for high-quality integration.
• Collaborate with post-silicon and manufacturing teams to validate features on silicon, support debug, and document lessons learned and design improvements.

Requirements

Must-have technical skills and experience required for initial consideration. Preferred items are listed separately.

• Hands-on DFT experience with tools such as Siemens Tessent, Spyglass, Fusion Compiler, and/or VCS (practical experience expected).
• Experience with scan insertion, low-coverage debug, GLS debug, and/or post-silicon debug.
• Experience generating test content and qualification vectors for manufacturing and ATE workflows.
• Ability to analyze and optimize logic for timing, power, area, and testability trade-offs.
• Strong debugging skills and experience resolving RTL/verification failures.

Nice-to-have:

• Experience with automatic test equipment (ATE) and HVM test content generation.
• Demonstrated collaboration and communication skills across cross-functional teams.
• Experience driving DFT methodology improvements and process innovations.

Education Requirements

BS in Electrical Engineering, Computer Engineering, or a related STEM field with 3+ years of relevant DFT experience OR MS in Electrical Engineering, Computer Engineering, or a related STEM field with 1+ year of relevant DFT experience. The posting also indicates equivalent qualifications may be met through industry experience, internships, coursework, or research.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.