Experienced DFT ATPG Engineer

Job Title

Experienced DFT ATPG Engineer

Role Summary

The DFT (Design for Test) ATPG Engineer designs and implements test and DFT features for IP blocks and SoCs, focusing on RTL coding, simulation, test content generation, and timing-closure support. The role works within the Data Center Group (DCG) cross-functional teams to ensure DFT integration, verification, and manufacturability.

Primary mission: deliver robust scan/MBIST/BSCAN solutions, high-volume manufacturing (HVM) test content for ATE, and post-silicon debug support to meet quality, test coverage, and production ramp targets.

Experience Level

Mid-level. Role expects professional DFT experience (typically 1+ years in tool use and DFT flow; degree-to-experience tradeoffs described in Education Requirements).

Responsibilities

Key responsibilities include DFT design, verification, integration, and production test support:

• Develop RTL and structural code to integrate DFT features (SCAN, MBIST, BSCAN, TAP, proc monitors, in-system test/BIST).
• Create test content for high-volume manufacturing (HVM) and support automatic test equipment (ATE) bring-up and production ramp.
• Provide DFT timing-closure support and optimize logic for power, performance, area, timing, test coverage, DPM, and reduced test time/vector memory.
• Review and drive verification plans for DFT features; run simulations and resolve failing RTL tests to ensure correctness.
• Integrate DFT blocks into functional IP and SoC; support SoC customers to ensure high-quality integration.
• Collaborate with post-silicon and manufacturing teams to verify features on silicon, support debug activities, and document learnings and design improvements.
• Drive high structural coverage through targeted IP tests and DFT methodologies.

Requirements

Must-have technical skills and practical experience. Preferred items are listed separately.

• Hands-on experience with industry DFT tools such as Siemens Tessent, SpyGlass, Fusion Compiler, and/or VCS.
• Experience with scan insertion, low-coverage debug, GLS debug, and/or post-silicon debug workflows.
• Proven RTL coding and simulation skills relevant to DFT integration and test content generation.
• Familiarity with fault coverage analysis, test memory/vector optimization, and strategies to reduce test time and improve DPM.
• Ability to collaborate with cross-functional teams (design, verification, manufacturing, post-silicon) and document results clearly.

Nice-to-have:

• Experience with automatic test equipment (ATE) and test content generation for high-volume manufacturing.
• Demonstrated problem-solving skills and a track record of process or methodology improvements in DFT.

Education Requirements

BS in Electrical Engineering, Computer Engineering, or related STEM field (with ~3+ years relevant DFT experience) OR MS in EE/CE or related STEM field (with ~1+ year relevant DFT experience). Equivalent practical experience may be accepted in lieu of degree. Fields cited include EE and CE; related technical STEM backgrounds are acceptable.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.