Engineer, Design Verification

Job Title

Engineer, Design Verification

Role Summary

Responsible for end-to-end verification of complex digital IPs and subsystems for SoC integration, from specification through sign-off. Works within the verification team and collaborates with RTL, architecture, emulation, and SoC verification groups to ensure design quality and integration readiness.

Experience Level

Entry-level - 1 to 2 years of relevant SoC verification experience.

Responsibilities

Key responsibilities include:

• Plan and execute IP- and subsystem-level verification from specification to sign-off.
• Define verification strategies, test plans, coverage models, and closure criteria.
• Develop scalable, reusable UVM-based verification environments and testbenches.
• Drive functional, code, assertion, and cross-coverage closure with measurable metrics.
• Apply AI/ML-assisted techniques to accelerate coverage convergence and optimize regressions.
• Implement constraint-random and directed test methodologies for protocol, corner-case, and stress scenarios.
• Collaborate with RTL, architecture, emulation, and SoC teams to ensure seamless integration.
• Develop checkers, scoreboards, assertions (SVA), and protocol monitors.
• Engage with EDA vendors to evaluate verification, coverage, and analytics tools.
• Support gate-level simulation, low-power verification, and post-silicon debug as required.

Requirements

Must-have technical skills and experience:

• 1–2 years in SoC verification domains with hands-on use of industry-standard EDA toolkits.
• Strong expertise in UVM-based testbench architecture and development.
• Proven experience in metric-driven verification, including functional and code coverage closure.
• Deep knowledge of SystemVerilog, UVM, and assertions (SVA).
• Experience with directed and constrained-random verification methodologies.
• Experience debugging complex issues in simulation, emulation, and post-silicon environments.
• Proficiency in Verilog/SystemVerilog; working knowledge of C/C++ and shell scripting.
• Strong analytical, problem-solving, and communication skills.

Nice-to-have:

• Hands-on experience with AI/ML-based verification tools (coverage gap analysis, stimulus optimization, regression triage).
• Scripting experience in Python, Perl, or TCL for automation and analytics.
• Exposure to formal verification and hybrid formal-simulation flows.
• Familiarity with high-speed or complex IPs (for example H.264), security, debug, or safety-critical domains.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.