Engineer, Advanced Packaging Development - Design Enablement & Layout

Job Title

Engineer, Advanced Packaging Development - Design Enablement & Layout

Role Summary

Work on advanced packaging design enablement and layout to support technology and product development. Partner with Process Integration, Product Engineering, Design, and Mask teams to define design rules, create test vehicles, and validate designs on silicon.

The role focuses on developing design rules and test structures, performing layout and DBR designs, enabling robust DRC flows, and using data analysis and AI to accelerate development.

Experience Level

Entry-level / Early Career. Requires at least 2 years of semiconductor industry experience in areas such as Process Integration, Yield Enhancement, Product Engineering, Design, Test Structure Development, or Unit Process Development.

Responsibilities

Key responsibilities include design-rule development, layout creation, validation, and cross-team coordination.

• Develop and refine design rules, requirements, and test structures for advanced packaging.
• Create layout and DBR test vehicles and product designs to support technology development.
• Ensure robust Design Rule Checks (DRC) and define responses to deviations.
• Analyze large datasets to extract insights and support data-driven decisions.
• Apply AI techniques to reduce development time and improve workflows.
• Manage structure evaluation to quantify process margins and support development.
• Partner with cross-functional teams to resolve process issues related to layout and prioritize solutions.
• Document and communicate complex problem resolutions and align design rules across nodes.
• Maintain effective communication with Process Integration, Product Engineering, Design, and Advanced Mask teams.

Requirements

Must-have technical skills and experience.

• Minimum 2+ years semiconductor industry experience in Process Integration, Yield/Product Engineering, Design, test-structure development, or unit-process development.
• Practical understanding of semiconductor memory process flows and TSV-based packaging.
• Hands-on experience with EDA/layout and verification tools such as Cadence Virtuoso (layout and schematic), Calibre, and Hspice.
• Familiarity with design-rule characterization and validation on silicon.
• Proficiency in programming for data analysis and automation (Python, R, or MATLAB).
• Experience analyzing large datasets and performing data post-processing and database/reticle data transfer.
• Ability to resolve complex technical issues and communicate clearly across engineering teams and CAD groups.

Nice-to-have:

• Experience coding in SKILL or SVRF.
• Experience using AI tools in layout design or AI agentic workflows.

Education Requirements

Bachelor's, Master's, or PhD in Electrical Engineering, Microelectronics, Physics, or a related technical field.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.