Distinguished Engineer, Verification

Role Summary

The Distinguished Engineer for Verification will work under the Marvell Data Center Design Verification Team to ensure the accuracy and performance of circuit designs within our chips. These designs cater to clients across sectors such as AI, cloud data centers, and telecommunications, where high-speed data transfer is critical.

Experience Level

Candidates should possess significant experience in SoC verification, with a total of at least 17 years in related professional domains. Alternatively, candidates holding a master's degree in any relevant field should have 12 to 15 years, while those with a PhD should have between 10 to 12 years of relevant experience.

Responsibilities

The role involves architecting and implementing simulation test benches using UVM, developing and executing test plans, debugging simulation failures, collaborating closely with logic designers, and mentoring less experienced engineers to ensure successful project outcomes.

Requirements

Applicants must demonstrate strong design knowledge and practical experience in verification environments, including UVM, System Verilog, C/C++, and DPI. Additionally, effective teamwork and problem-solving skills, along with a detail-oriented approach, are essential.

Education Requirements

A Bachelor’s Degree in Computer Science, Electrical Engineering, or a related discipline is required. Higher degrees such as a Master’s or PhD are recognized, with various experience levels specified above in the Experience Level section.